The present invention relates to a semiconductor device, to which chip-size packaging is applied, and a manufacturing method therefor.
Various type semiconductor chip packaging structures have been proposed. With miniaturization of packaged chips, for example, what is called a chip-size packaging structure has been proposed, in which a rewiring layer (i.e., a wiring layer for packaging) is formed, on a passivation layer (i.e., a protection layer) of a device-forming surface of a semiconductor chip.
According to the chip-size packaging, a method has been proposed, in which, for example, an electric connection member such as a bump is formed on each of electric connection members by a bonding-wire, and in which a packaging device (i.e., a semiconductor device) is then formed by forming a rewiring layer connected to each of the electric connection members (see, for example, Patent Document 1).
[Patent Document 1] JP-A-9-64049
However, the method proposed in Patent Document 1 (i.e., JP-A-9-64049) has a problem that when a rewiring layer is formed on the electric connection member formed by bonding, it is necessary to adjust a height (i.e., perform leveling) of the electric connection member.
For example, the electric connection member (e.g., a bump) formed by a bonding-wire is formed using, e.g., a wire bonder. The connection of the bonding-wire to an electrode pad, and the cutting of the connected bonding-wire are consecutively performed to thereby form the electric connection member.
Accordingly, the bump formed by the bonding-wire varies in height from a bump-forming surface (i.e., the electrode pad). This makes it difficult to form a rewiring layer to be connected to the bump, without changing the bump. Consequently, a process of applying a predetermined load to the bump so as to planarize the bump is needed.
Such planarization of the bump is usually performed on a wafer (i.e., before the wafer is diced into individual chips). However, a problem occurs, in which when the planarization of many bumps formed on a wafer surface of, for example, a recent mainstream wafer having a diameter of 300 mm, the variation in the height of the bump increases.
Another problem occurs, in which, for example, when the variation in the height of the bump increases, variation in the connection state between the bump and a rewiring layer connected to the bump occurs, so that the reliability of a semiconductor device (i.e., a packaging device) is degraded.
Additionally, according to the method disclosed in patent Document 1 (i.e., JP-A-9-64049), an insulating layer is formed to cover the bump. Accordingly, a polishing process of polishing the insulating layer is required to expose the bump. To form a rewiring layer upon completion of polishing-process, a process of desmearing a surface of the insulating layer (i.e., what is called a desmear process) is needed. Consequently, a process for forming a plating layer is complicated. This causes increase in cost of manufacturing a semiconductor device (i.e., a packaging device).
Although an electrically conductive layer can be formed by a sputtering method or a CVD method, these methods require costly film-forming apparatuses. This leads to increase in cost of manufacturing. Consequently, these methods are impractical.